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| 1 www.fairchildsemi.com ace1202 product family rev. b.1 ace1202 product family arithmetic controller engine (acex?) for low power applications ace1202 product family arithmetic controller engine (acex?) for low power applications general description the ace1202 (arithmetic controller engine) family of microcontrollers is a dedicated programmable monolithic inte- grated circuit for applications requiring high performance, low power, and small size. it is a fully static part fabricated using cmos technology. the ace1202 product family has an 8-bit microcontroller core, 64 bytes of ram, 64 bytes of data eeprom and 2k bytes of code eeprom. its on-chip peripherals include a multi-function 16-bit timer, watchdog/idle timer, and programmable undervoltage de- tection circuitry. the on-chip clock and reset functions reduce the number of required external components. the ace1202 product family is available in 8- and 14-pin soic and dip packages. features arithmetic controller engine 2k bytes on-board code eeprom 64 bytes data eeprom 64 bytes ram instruction set geared for block encryption watchdog multi-input wake-up on all i/o pins 16-bit multifunction timer with difference capture 12-bit idle timer block and connection diagram preliminary august 2001 hardware bit - coder (hbc) (ace1202-2 only) on-chip oscillator ?no external components ?1 s instruction cycle time on-chip power-on reset programmable read and write disable functions memory mapped i/o multilevel low voltage detection brown-out reset software selectable i/o option ?push-pull outputs with tri-state option ? weak pull-up or high impedance fully static cmos ?low power halt mode (100na @ 3.3v) ?power saving idle mode single supply operation ?1.8-5.5v (p.n. ace1202l) ?2.2-5.5v (p.n. ace1202, ace12022) ?2.7-5.5v (p.n. ace1202b, ace12022b) 40 years data retention 1,000,000 data changes 8 and 14-pin soic, 8 and 14-pin dip packages. (csp package available upon request) in-circuit programming vcc 1 power-on reset brown-out reset/low battery detect ace1202 core (4 interrupt sources and vectors) programming interface 2k bytes of code eeprom 64 bytes of data eeprom 64 bytes of ram 12-bit timer0 with watchdog timer 16-bit multi-function timer1 with difference capture halt & idle power saving modes gport general purpose i/o with multi- input wakeup internal oscillator gnd 1 reset 2 (cko) g0 (cki) g1 (t1/tx 3 ) g2 g4 (tx 3 ) g5 g6 2 g7 2 (input only) g3 hardware bit-coder 3 ? 2001 fairchild semiconductor corporation 1. 100nf decoupling capacitor recommended 2. available only in the 14-pin package option 3. available only on the ace1202-2 device
2 www.fairchildsemi.com ace1202 product family rev. b.1 ace1202 product family arithmetic controller engine (acex?) for low power applications v cc v cc optional led rf stage rf interface g0 g1 g5 g2 gnd g4 g3 figure 2: acex application example (remote keyless entry) load vcc gnd sft_out cki 1 2 3 45 6 7 8 sft_in nc/vcc nc g3 vcc gnd g1 1 2 3 4 5 6 78 g4 nc 9 10 11 12 13 14 g6 g7 g5 nc nc g2 reset g0 g3 vcc gnd g2 g1 1 2 3 45 6 7 8 g4 g0 g5 load vcc gnd cki 1 2 3 4 5 6 78 sft_in nc nc 9 10 11 12 13 14 nc nc nc/vcc nc nc sft_out reset figure 3: ace1202/ace1202-2 8-pin device pinout b) programming mode operation figure 4: ace1202/ace1202-2 14-pin device pinout b) programming mode operation a) normal mode operation a) normal mode operation 3 www.fairchildsemi.com ace1202 product family rev. b.1 ace1202 product family arithmetic controller engine (acex?) for low power applications absolute maximum ratings ambient storage temperature -65 c to +150 c input voltage not including g3 -0.3v to v cc +0.3v g3 input voltage 0.3v to 13v lead temperature (10s max) +300 c electrostatic discharge on all pins 2000v min operating conditions relative humidity (non-condensing) 95% eeprom write limits see dc electrical characteristics 2.0 electrical characteristics part number operating voltage ambient operating temperature ace1202 2.2 to 5.5v 0 c to 70 c ace12022 2.2 to 5.5v 0 c to 70 c ace1202e 2.2 to 5.5v -40 c to +85 c ace12022e 2.2 to 5.5v -40 c to +85 c ace1202v 2.2 to 5.5v -40 c to +125 c ace1202b 2.7 to 5.5v 0 c to 70 c ace12022b 2.7 to 5.5v 0 c to 70 c ace1202be 2.7 to 5.5v -40 c to +85 c ace12022be 2.7 to 5.5v -40 c to +85 c ace1202bv 2.7 to 5.5v -40 c to +125 c ace12022bv 2.7 to 5.5v -40 c to +125 c ace1202l 1.8 to 5.5v 0 c to 70 c 4 www.fairchildsemi.com ace1202 product family rev. b.1 ace1202 product family arithmetic controller engine (acex?) for low power applications preliminary ace1202/ace1202-2 dc electrical characteristics v cc = 1.8/2.2/2.7 to 5.5v all measurements valid for ambient operating temperature range unless otherwise stated. symbol parameter conditions min typ max units i cc 4 supply current 1.8v 0.2 0.5 ma no data eeprom write in 2.2v 0.4 1.0 ma progress 2.7v 0.7 1.2 ma 3.3v 1.2 2.0 ma 5.5v 3.7 5.5 ma i cch halt mode current 3.3v @ -40 c to +25 c 10 100 na 5.5v @ -40 c to +25 c 60 1000 na 3.3v @ +85 c 75 1000 na 5.5v @ +85 c 400 2500 na 3.3v @ +125 c 600 5000 na 5.5v @+125 c 1550 8000 na i ccl 5 idle mode current 3.3v 150 200 a 5.5v 200 300 a v ccw eeprom write voltage code eeprom in 4.5 5.0 5.5 v programming mode data eeprom in 2.4 5.5 v operating mode s vcc power supply slope 1 s/v 10ms/v v il input low with schmitt v cc = 1.8 -5.5v 0.2v cc v trigger buffer v ih input high with schmitt v cc = 1.8 - 5.5v 0.8v cc v trigger buffer i ip input pull-up current v cc =5.5v, v in =0v 30 65 350 a i tl tri-state leakage v cc =5.5v 2 200 na v ol output low voltage v cc = 1.8 - 2.2v g0, g1, g2, g4, g6, g7 0.8 ma sink 0.2v cc v g5 1.0 ma sink 0.2v cc v output low voltage v cc = 2.2v 3.3v g0, g1, g2, g4, g6, g7 3.0 ma sink 0.2v cc v g5 5.0 ma sink 0.2v cc v output low voltage v cc = 3.3v 5.5v g0, g1, g2, g4, g6, g7 5.0 ma sink 0.2v cc v g5 10.0 ma sink 0.2v cc v v oh output high voltage v cc = 1.8 - 2.2v g0, g1, g2, g4, g6, g7 0.1 ma source 0.8v cc v g5 0.2 ma source 0.8v cc v output high voltage v cc = 3.3v 5.5v g0, g1, g2, g4, g6, g7 0.4 ma source 0.8v cc v g5 0.8 ma source 0.8v cc v output high voltage v cc = 3.3v 5.5v g0, g1, g2, g4, g6, g7 0.4 ma source 0.8v cc v g5 1.0 ma source 0.8v cc v 4 i cc active current is dependent on the program code. 5 based on a continuous idle looping program. 5 www.fairchildsemi.com ace1202 product family rev. b.1 ace1202 product family arithmetic controller engine (acex?) for low power applications preliminary ace1202/ace1202-2 ac electrical characteristics v cc = 1.8/2.2/2.7 to 5.5v all measurements valid for ambient operating temperature range unless otherwise stated. parameter conditions min typ max units instruction cycle time from 5.0v at +25 c 0.9 1.0 1.1 s internal clock - setpoint internal clock voltage dependent 3.0v to 5.5v, +5 % frequency variation constant temperature internal clock temperature 3.0v to 5.5v, +10 % dependent frequency variation full temperature range internal clock frequency 3.0v to 4.5v, +2 % deviation for 0.5v drop constant temperature crystal oscillator frequency (note 6) 4 mhz external clock frequency (note 7) 4 mhz eeprom write time 3 10 ms internal clock start up time (note 7) 2 ms oscillator start up time (note 7) 2400 cycles 6 the maximum permissible frequency is guaranteed by design but not 100% tested. 7 the parameter is guaranteed by design but not 100% tested. preliminary ace1202/ace1202-2 electrical characteristics for programming all data following is valid between 4.5v and 5.5v at ambient temperature. the following charac- teristics are guaranteed by design but are not 100% tested. see "eeprom write time" in the ac electrical characteristics for definition of the programming ready time. parameter description min max units t hi clock high time 500 dc ns t lo clock low time 500 dc ns t dis shift_in setup time 100 ns t dih shift_in hold time 100 ns t dos shift_out setup time 100 ns t doh shift_out hold time 900 ns t sv1 , t sv2 load supervoltage timing 50 s t load1 , t load2 , t load3 , t load4 load timing 5 s v supervoltage supervoltage level 11.5 12.5 v 6 www.fairchildsemi.com ace1202 product family rev. b.1 ace1202 product family arithmetic controller engine (acex?) for low power applications preliminary ace1202/ace1202-2 low battery detect (lbd) characteristics v cc = 2.2/1.8 to 5.5v the following characteristics are guaranteed by design but are not 100% tested. parameter conditions min typ max units lbd voltage threshold level 1 @ -40 c 2.84 v level 8 @ -40 c 2.02 v level 1 @ 0 c 2.98 v level 8 @ 0 c 2.05 v level 1 @ -25 c 3.08 v level 8 @ +25 c 2.12 v level 1 @ +85 c 3.31 v level 8 @ +85 c 2.27 v level 1 @ +125 c 3.36 v level 8 @ +125 c 2.40 v preliminary ace1202/ace1202-2 brown-out reset (bor) characteristics v cc = 2.2 to 5.5v the following characteristics are guaranteed by design but are not 100% tested. parameter conditions min typ max units bor trigger threshold -40 c 1.98 v 0 c 2.06 v +25 c 2.12 v +85 c 2.27 v +125 c 2.37 v preliminary ace1202l brown-out reset (bor) characteristics v cc = 1.8 to 5.5v the following characteristics are guaranteed by design but are not 100% tested. parameter conditions min typ max units bor trigger threshold 0 c 1.78 v +25 c 1.82 v +70 c 1.96 v 7 www.fairchildsemi.com ace1202 product family rev. b.1 ace1202 product family arithmetic controller engine (acex?) for low power applications 3.0 ac & dc electrical characteristic graphs figure 5: rc oscillator frequency vs. temperature (v cc =5.0v) 1.000 1.200 1.400 1.600 1.800 2.000 2.200 2.400 2.600 3.3k/82pf 5.6k/100pf 6.8k/100pf avg min max frequency (mhz) 0.600 0.800 1.000 1.200 1.400 1.600 3.3k/82pf 5.6k/100pf 6.8k/100pf avg min max frequency (mhz) resistor & capacitor values [k & pf] figure 6: rc oscillator frequency vs. temperature(v cc =2.5v) frequency (mhz) temperature [ c] figure 7: internal oscillator frequency resistor & capacitor values [k & pf] 8 www.fairchildsemi.com ace1202 product family rev. b.1 ace1202 product family arithmetic controller engine (acex?) for low power applications t s min t s actual t s max time v cc v batt 1v figure 8: power supply rise time name parameter unit v cc supply voltage [v] v batt battery voltage (nominal operating voltage) [v] t s min minimum time for v cc to rise by 1v [ms] t s actual actual time for v cc to rise by 1v [ms] t s max maximum time for v cc to rise by 1v [ms] s vcc power supply slope [ms/v] 9 www.fairchildsemi.com ace1202 product family rev. b.1 ace1202 product family arithmetic controller engine (acex?) for low power applications figure 9: i cc active icc active (ma) temperature [ c] icc active (ma) i cc active (data eeprom writes) vs. temperature temperature [ c] i cc active (no data eeprom writes) vs. temperature 10 www.fairchildsemi.com ace1202 product family rev. b.1 ace1202 product family arithmetic controller engine (acex?) for low power applications figure 10: halt mode currents temperature [ c] icc halt (na) halt current vs. temperature 11 www.fairchildsemi.com ace1202 product family rev. b.1 ace1202 product family arithmetic controller engine (acex?) for low power applications icc idle ( a) figure 11: idle mode currents idle current vs. temperature temperature [ c] 12 www.fairchildsemi.com ace1202 product family rev. b.1 ace1202 product family arithmetic controller engine (acex?) for low power applications 4.0 arithmetic controller core the acex microcontroller core is specifically designed for low cost applications involving bit manipulation, shifting and block encryption.it is based on a modified harvard architecture meaning peripheral, i/o, and ram locations are addressed separately from instruction data. the core differs from the traditional harvard architecture by aligning the data and instruction memory sequentially. this allows the x-pointer (12-bits) to point to any memory location in either figure 12: programming model segment of the memory map. this modification improves the overall code efficiency of the acex microcontroller and takes advantage of the flexibility found on von neumann style ma- chines. 4.1 cpu registers the acex microcontroller has five general-purpose registers. these registers are the accumulator (a), x-pointer (x), program counter (pc), stack pointer (sp), and status register (sr). the x, sp, and sr registers are all memory-mapped. 8-bit accumulator register 12-bit x pointer register 11-bit program counter 4-bit stack pointer 8-bit status register negative flag half carry flag (from bit 3) carry flag (from msb) zero flag global interrupt mask ready flag (from eeprom) a x pc sp sr 0 0 0 0 n h c z g 0 0 r 7 11 10 3 13 www.fairchildsemi.com ace1202 product family rev. b.1 ace1202 product family arithmetic controller engine (acex?) for low power applications 4.1.1 accumulator (a) the accumulator is a general-purpose 8-bit register that is used to hold data and results of arithmetic calculations or data manipulations. 4.1.2 x-pointer (x) the x-pointer register allows for a 12-bit indexing value to be added to an 8-bit offset creating an effective address used for reading and writing between the entire memory space. (software can only read from code eeprom.) this provides software with the flexibility of storing lookup tables in the code eeprom memory space for the core s accessibility during normal operation. the acex core allows software to access the entire 12-bit x-pointer register using the special x-pointer instructions (e.g. ld x, #000h). (see table 9) however, software may also access the register through any of the memory-mapped instructions using the xhi (x[11:8]) and xlo (x[7:0]) variables located at 0xbe and 0xbf, respectively. (see table 11) the x register is divided into two sections. the 11 least significant bits (lsbs) of the register is the address of the program or data memory space. the most significant bit (msb) of the register is write only and selects between the data (0x000 to 0x0ff) or program (0x800 to 0xfff) memory space. example: if bit 11 = 0, then the ld a, [00,x] instruction will take a value from address range 0x000 to 0x0ff and load it into a. if bit 11 = 1, then the ld a, [00,x] instruction will take a value from address range 0x800 to 0xfff and load it into a. the x register can also serve as a counter or temporary storage register. however, this is true only for the 11-lsbs since the 12 th bit is dedicated for memory space selection. 4.1.3 program counter (pc) the 10-bit program counter register contains the address of the next instruction to be executed. after a reset, if in normal mode the program counter is initialized to 0x800. 4.1.4 stack pointer (sp) the acex microcontroller has an automatic program stack with a 4- bit stack pointer. the stack can be initialized to any location between addresses 0x30-0x3f. normally, the stack pointer is initialized by one of the first instructions in an application program. after a reset, the stack pointer is defaulted to 0xf pointing to address 0x3f. the stack is configured as a data structure which decrements from high to low memory. each time a new address is pushed onto the stack, the core decrements the stack pointer by two. each time an address is pulled from the stack, the core incre- ments the stack pointer is by two. at any given time, the stack pointer points to the next free location in the stack. when a subroutine is called by a jump to subroutine (jsr) instruction, the address of the instruction is automatically pushed onto the stack least significant byte first. when the subroutine is finished, a return from subroutine (ret) instruction is executed. the ret instruction pulls the previously stacked return address from the stack and loads it into the program counter. execution then continues at the recovered return address. 4.1.5 status register (sr) the 8-bit status register (sr) contains four condition code indicators (c, h, z, and n), one interrupt masking bit (g), and an eeprom write flag (r). the condition codes are automatically updated by most instructions. (see table 10) carry/borrow (c) the carry flag is set if the arithmetic logic unit (alu) performs a carry or borrow during an arithmetic operation and by its dedicated instructions. the rotate instruction operates with and through the carry bit to facilitate multiple-word shift operations. the ldc and invc instructions facilitate direct bit manipulation using the carry flag. half carry (h) the half carry flag indicates whether an overflow has taken place on the boundary between the two nibbles in the accumulator. it is primarily used for binary coded decimal (bcd) arithmetic calculation. zero (z) the zero flag is set if the result of an arithmetic, logic, or data manipulation operation is zero. otherwise, it is cleared. negative (n) the negative flag is set if the msb of the result from an arithmetic, logic, or data manipulation operation is set to one. otherwise, the flag is cleared. a result is said to be negative if its msb is a one. interrupt mask (g) the interrupt request mask (g) is a global mask that disables all maskable interrupt sources. if the g bit is cleared, interrupts can become pending, but the operation of the core continues uninter- rupted. however, if the g bit is set an interrupt is recognized. after any reset, the g bit is cleared by default and can only be set by a software instruction. when an interrupt is recognized, the g bit is cleared after the pc is stacked and the interrupt vector is fetched. once the interrupt is serviced, a return from interrupt instruction is normally executed to restore the pc to the value that was present before the interrupt occurred. the g bit is reset to one after a return from interrupt is executed. although the g bit can be set within an interrupt service routine, nesting interrupts in this way should only be done when there is a clear understanding of latency and of the arbitration mechanism. 4.2 interrupt handling when an interrupt is recognized, the current instruction completes its execution. the return address (the current value in the program counter) is pushed onto the stack and execution continues at the address specified by the unique interrupt vector (see table 11). this process takes five instruction cycles. at the end of the interrupt service routine, a return from interrupt (reti) instruction is executed. the reti instruction causes the saved address to be pulled off the stack in reverse order. the g bit is set and instruction execution resumes at the return address. table 8: interrupt priority sequence priority (4 highest, 1 lowest) interrupt 4 miw (edgei) 3 timer0 (tmri0) 2 timer1 (tmri1) 1 software (intr) 14 www.fairchildsemi.com ace1202 product family rev. b.1 ace1202 product family arithmetic controller engine (acex?) for low power applications the acex microcontroller is capable of supporting four interrupts. three are maskable through the g bit of the sr and the fourth (software interrupt) is not inhibited by the g bit (see figure 13). the software interrupt instruction is generated by the execution of the intr instruction. once the intr instruction is executed, the acex core will interrupt whether the g bit is set or not. the intr interrupt is executed in the same manner as the other maskable interrupts where the program counter register is stacked and the g bit is cleared. this means, if the g bit was enabled prior to the software interrupt the reti instruction must be used to return from interrupt in order to restore the g bit to its previous state. however, if the g bit was not enabled prior to the software interrupt the ret instruction must be used. in case of multiple interrupts occurring at the same time, the acex microcontroller core has prioritized the interrupts. the interrupt priority sequence in shown in table 8. 4.3 addressing modes the acex microcontroller has seven addressing modes indexed, indirect, direct, immediate, absolute jump, and relative jump. indexed the instruction allows an 8-bit unsigned offset value to be added to the 11-lsbs of the x-pointer yielding a new effective address. this mode can be used to address either data or program memory space. indirect the instruction allows the x-pointer to address any location within the data memory space. direct the instruction contains an 8-bit address field that directly points to the data memory space as an operand. immediate the instruction contains an 8-bit immediate field as an operand. inherent this instruction has no operands associated with it. absolute the instruction contains a 11-bit address that directly points to a location in the program memory space. there are two operands associated with this addressing mode. each operand contains a byte of an address. this mode is used only for the long jump (jmp) and jsr instructions. relative this mode is used for the short jump (jp) instructions where the operand is a value relative to the current pc address. with this instruction, software is limited to the number of bytes it can jump, -31 or +32. figure 13: basic interrupt structure t1pnd t0pnd wkpnd t1en t0int en wkint en g intr t1 t0 miw interrupt pending flags interrupt enable bits global interrupt enable interrupt interrupt source with priority 15 www.fairchildsemi.com ace1202 product family rev. b.1 ace1202 product family arithmetic controller engine (acex?) for low power applications table 9: instruction addressing modes instruction immediate direct indexed indirect inherent relative absolute adc a, # a, m a, [x] add a, # a, m a, [x] and a, # a, m a, [x] or a, # a, m a, [x] subc a, # a, m a, [x] xor a, # a, m a, [x] clr max inc max dec max ifeq a, # x, # m,# a, m a, [00,x] a, [x] ifgt a, # x, # a, m a, [00,x] a, [x] ifne a, # a, m a, [00,x] a, [x] iflt x, # sc no-op rc no-op ifc no-op ifnc no-op invc no-op ldc #, m stc #, m rlc ma rrc ma ld a, # x, # m, # a, m a, [00,x] a, [x] st a, m a, [00,x] a, [x] ld m, m nop no-op ifbit #, a #, m sbit #, m #, [x] rbit #, m #, [x] jp rel jsr [00,x] m jmp [00,x] m ret no-op reti no-op intr no-op 16 www.fairchildsemi.com ace1202 product family rev. b.1 ace1202 product family arithmetic controller engine (acex?) for low power applications mnemonic operand bytes cycles flags affected adc a, [x] 1 1 c,h,z,n adc a, m 2 2 c,h,z,n adc a, # 2 2 c,h,z,n add a, [x] 1 1 z,n add a, m 2 2 z,n add a, # 2 2 z,n and a, # 2 2 z,n and a, m 2 2 z,n and a, [x] 1 1 z,n clr x 1 1 z clr a 1 1 c,h,z,n clr m 2 2 c,h,z,n dec a 1 1 z,n dec m 2 2 z,n dec x 1 1 z ifbit #, a 1 1 none ifbit #, m 2 2 none ifc 1 1 none ifeq a, [00,x] 2 3 none ifeq a, [x] 1 1 none ifeq a, # 2 2 none ifeq a, m 2 2 none ifeq m, # 3 3 none ifeq x, # 3 3 none ifgt a, # 2 2 none ifgt a, [00,x] 2 3 none ifgt a, [x] 1 1 none ifgt a, m 2 2 none ifgt x, # 3 3 none ifne a, # 2 2 none ifne a, [00,x] 2 3 none ifne a, [x] 1 1 none ifne a, m 2 2 none iflt x, # 3 3 none ifnc 1 1 none inc a 1 1 z,n inc m 2 2 z,n inc x 1 1 z intr 1 5 none invc 1 1 c mnemonic operand bytes cycles flags affected jmp m 3 4 none jmp [00,x] 2 3 none jp 1 1 none jsr m 3 5 none jsr [00,x] 2 5 none ld a, # 2 2 none ld a, [00,x] 2 3 none ld a, [x] 1 1 none ld a, m 2 2 none ld m, # 3 3 none ld x, # 3 3 none ldc #, m 2 2 c ld m, m 3 3 none nop 1 1 none or a, # 2 2 z,n or a, [x] 1 1 z,n or a, m 2 2 z,n rbit #, [x] 1 2 z,n rbit #, m 2 2 z,n rc 1 1 c,h ret 1 5 none reti 1 5 none rlc a 1 1 c,z,n rlc m 2 2 c,z,n rrc a 1 1 c,z,n rrc m 2 2 c,z,n sbit #, [x] 1 2 z,n sbit #, m 2 2 z,n sc 1 1 c,h st a, [00,x] 2 3 none st a, [x] 1 1 none st a, m 2 2 none stc #, m 2 2 z,n subc a, # 2 2 c,h,z,n subc a, [x] 1 1 c,h,z,n subc a, m 2 2 c,h,z,n xor a, # 2 2 z,n xor a, [x] 1 1 z,n xor a, m 2 2 z,n table 10: instruction cycles and bytes 17 www.fairchildsemi.com ace1202 product family rev. b.1 ace1202 product family arithmetic controller engine (acex?) for low power applications 4.4 memory map all i/o ports, peripheral registers and core registers, except the accumulator and the program counter are mapped into memory s pace. table 11: memory map address memory space block contents 0x00 - 0x3f data sram data ram 0x40 - 0x7f data eeprom data eeprom 0xa0 data hbc hbcntrl register (ace1202-2 only) 0xa1 data hbc pscale register (ace1202-2 only) 0xa2 data hbc hpattern register (ace1202-2 only) 0xa3 data hbc lpattern register (ace1202-2 only) 0xa4 data hbc bpsel register (ace1202-2 only) 0xa9 data hbc dat0 register (ace1202-2 only) 0xaa data timer1 t1ralo register 0xab data timer1 t1rahi register 0xac data timer1 tmr1lo register 0xad data timer1 tmr1hi register 0xae data timer1 t1cntrl register 0xaf data miw wkedg register 0xb0 data miw wkpnd register 0xb1 data miw wken register 0xb2 data i/o portgd register 0xb3 data i/o portgc register 0xb4 data i/o portgp register 0xb5 data timer0 wdsvr register 0xb6 data timer0 t0cntrl register 0xb7 data clock halt mode register 0xb8 - 0xbc reserved 0xbd data lbd lbd register 0xbe data core xhi register 0xbf data core xlo register 0xc0 data core power mode clear (pmc) register 0xce data core sp register 0xcf data core status register (sr) 0x800 - 0xff5 program eeprom code eeprom 0xff6 - 0xff7 program core timer0 interrupt vector 0xff8 - 0xff9 program core timer1 interrupt vector 0xffa - 0xffb program core miw interrupt vector 0xffc - 0xffd program core software interrupt vector 0xffe - 0xfff reserved 18 www.fairchildsemi.com ace1202 product family rev. b.1 ace1202 product family arithmetic controller engine (acex?) for low power applications 4.5 memory the acex microcontroller device has 64 bytes of sram and 64 bytes of eeprom available for data storage. the device also has 2k bytes of eeprom for program storage. software can read and write to sram and data eeprom but can only read from the code eeprom. while in normal mode, the code eeprom is protected from any writes. the code eeprom can only be rewritten when the device is in program mode and if the write disable (wdis) bit of the initialization register is not set to 1. while in normal mode, the user can write to the data eeprom array by 1) polling the ready (r) flag of the sr, then 2) executing the appropriate instruction. if the r flag is 1, the data eeprom block is ready to perform the next write. if the r flag is 0, the data eeprom is busy. the data eeprom array will reset the r flag after the completion of a write cycle. attempts to read, write, or enter halt/idle mode while the data eeprom is busy (r = 0) can affect the current data being written. 4.6 initialization registers the acex microcontroller has two 8-bit wide initialization regis- ters. these registers are read from the memory space on power- up to initialize certain on-chip peripherals. figure 14 provides a detailed description of initialization register 1. the initialization register 2 is used to trim the internal oscillator to its appropriate frequency. this register is pre-programmed in the factory to yield an internal instruction clock of 1mhz. both initialization registers 1 and 2 can be read from and written to during programming mode. however, re-trimming the internal oscillator (writing to the initialization register 2) once it has left the factory is discouraged . figure 14: initialization register 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cmode[0] cmode[1] wden boren blsel 10 ubd 8,9 wdis 8,9 rdis 8,9 (0) rdis 8,9 if set, disables attempts to read the contents from the memory while in programming mode (1) wdis 8,9 if set, disables attempts to write new contents to the memory while in programming mode (2) ubd 8,9 if set, the device will not allow any writes to occur in the upper block of data eeprom (0x60-0x7f) (3) blsel 10 if set, the brown-out reset (bor) voltage reference level is set to its higher range for p.n. ace1202/ace12022 if not set, the bor voltage reference level is set to its lower range for p.n. ace1202l (4) boren if set, allows a bor to occur if vcc falls below the voltage reference level (5) wden if set, enables the on-chip processor watchdog circuit (6) cmode[1] clock mode select bit 1 (see table 17) (7) cmode[0] clock mode select bit 0 (see table 17) 8 if both the wdis and rdis bits are set, the device will no longer be able to be placed into program mode. 9 if the rdis or ubd bits are not set while the wdis bit is not set, then the rdis and ubd bits can be reset. 10 the blsel bit is set to its appropriate level in the factory. if writing to the initialization register is necessary, be sure to maintain blsel set value. 19 www.fairchildsemi.com ace1202 product family rev. b.1 ace1202 product family arithmetic controller engine (acex?) for low power applications 5.0 timer 1 timer 1 is a versatile 16-bit timer that can operate in one of four modes: pulse width modulation (pwm) mode, which generates pulses of a specified width and duty cycle external event counter mode, which counts occurrences of an external event standard input capture mode, which measures the elapsed time between occurrences of external events difference input capture mode, which automatically measures the difference between edges timer 1 contains a 16-bit timer/counter register (tmr1), a 16-bit auto-reload/capture register (t1ra), and an 8-bit control register (t1cntrl). all register are memory-mapped for simple access through the core with both the 16-bit registers organized as a pair of 8-bit register bytes {tmr1hi, tmr1lo} and {t1rahi, t1ralo}. depending on the operating mode, the timer contains an external input or output (t1) that is multiplexed with the i/o pin g2. by default, the tmr1 is reset to 0xffff, t1ra is reset to 0x0000, and t1cntrl is reset to 0x00. the timer can be started or stopped through the t1cntrl register bit t1c0. when running, the timer counts down (decre- ments) every clock cycle. depending on the operating mode, the timer s clock is either the instruction clock or a transition on the t1 input. in addition, occurrences of timer underflow (transitions from 0x0000 to 0xffff/t1ra value) can either generate an interrupt and/or toggle the t1 output pin. timer 1 s interrupt (tmri1) can be enabled by interrupt enable (t1en) bit in the t1cntrl register. when the timer interrupt is enabled, depending on the operating mode, the source of the interrupt is a timer underflow and/or a timer capture. 5.1 timer control bits reading and writing to the t1cntrl register controls the timer s operation. by writing to the control bits, the user can enable or disable the timer interrupts, set the mode of operation, and start or stop the timer. the t1cntrl register bits are described in tables 12 and 13. table 12: timer1 control register (t1cntrl) t1cntrl register name function bit 7 t1c3 timer timer1 control bit 3 (see table 13) bit 6 t1c2 timer timer1 control bit 2 (see table 13) bit 5 t1c1 timer timer1 control bit 1 (see table 13) bit 4 t1c0 timer timer1 run: 1 = start timer, 0 = stop timer; or timer timer1 underflow interrupt pending flag in input capture mode bit 3 t1pnd timer1 interrupt pending flag: 1 = timer1 interrupt pending, 0 = timer1 interrupt not pending bit 2 t1en timer1 interrupt enable bit: 1 = timer1 interrupt enabled, 0 = timer1 interrupt disabled bit 1 m4s1 capture type: 0 = pulse capture, 1 = cycle capture (see table 13) bit 0 ----------- reserved table 13: timer1 operating modes t1 t1 t1 m4 timer mode interrupt a timer counts on c3 c2 c1 s1 source 0 0 0 x mode 2 timer1 underflow t1 pos. edge 0 0 1 x mode 2 timer1 underflow t1 neg. edge 1 0 1 x mode 1 t1 toggle autoreload t1ra instruction clock 1 0 0 x mode 1 no t1 toggle autoreload t1ra instruction clock 0 1 0 x mode 3 captures: t1 pos. edge pos. t1 edge instruction clock 0 1 1 x mode 3 captures: t1 neg. edge neg. t1 edge instruction clock 1 1 0 0 mode 4 difference capture pos. to neg. instruction clock 1 1 0 1 mode 4 difference capture pos. to pos. instruction clock 1 1 1 0 mode 4 difference capture neg. to pos. instruction clock 1 1 1 1 mode 4 difference capture neg. to neg. instruction clock 20 www.fairchildsemi.com ace1202 product family rev. b.1 ace1202 product family arithmetic controller engine (acex?) for low power applications 5.2 mode 1: pulse width modulation (pwm) mode in the pwm mode, the timer counts down at the instruction clock rate. when an underflow occurs, the timer register is reloaded from t1ra and the count down proceeds from the loaded value. at every underflow, a pending flag (t1pnd) located in the t1cntrl regis- ter is set. software must then clear the t1pnd flag and load the t1ra register with an alternate pwm value. in addition, the timer can be configured to toggle the t1 output bit upon underflow. configuring the timer to toggle t1 results in the generation of a signal outputted from port g2 with the width and duty cycle controlled by the values stored in the t1ra. a block diagram of the timer s pwm mode of operation is shown in figure 15. the timer has one interrupt (tmri1) that is maskable through the t1en bit of the t1cntrl register. however, the core is only interrupted if the t1en bit and the g (global interrupt enable) bit of the sr is set. if interrupts are enabled, the timer will generate an interrupt each time t1pnd flags is set (whenever the timer underflows provided that the pending flag was cleared.) the interrupt service routine is responsible for proper handling of the t1pnd flag and the t1en bit. the interrupt will be synchronous with every rising and falling edge of the t1 output signal. generating interrupts only on rising or falling edges of t1 is achievable through appropriate handling of the t1en bit or t1pnd flag through software. the following steps show how to properly configure timer 1 to operate in the pwm mode. for this example, the t1 output signal is toggled with every timer underflow and the high and low times for the t1 output can be set to different values. the t1 output signal can start out either high or low depending on the configuration of g2; the instructions below are for starting with the t1 output high. follow the instructions in parentheses to start the t1 output low. data bus 16-bit auto-reload register (t1ra) 16-bit timer (tmr1) data latch t1 underflow interrupt instruction clock figure 15: pulse width modulation mode 1. configure t1 as an output by setting bit 2 of portgc. - sbit 2, portgc ; configure g2 as an output 2. initialize t1 to 1 (or 0) by setting (or clearing) bit 2 of portgd. - sbit 2, portgd ; set g2 high 3. load the initial pwm high (low) time into the timer register. - ld tmr1lo, #6fh ; high (low) for 1.391ms (1mhz clock) - ld tmr1hi, #05h 4. load the pwm low (high) time into the t1ra register. - ld t1ralo, #2fh ; low (high) for .303ms (1mhz clock) - ld t1rahi, #01h 5. write the appropriate control value to the t1cntrl register to select pwm mode with t1 toggle, to clear the enable bit and pending flag, and to start the timer. (see table 12 and 13) - ld t1cntrl, #0b0h ; setting the t1c0 bit starts the timer 6. after every underflow, load t1ra with alternate values. if the user wishes to generate an interrupt on a t1 output transition, reset the pending flags and then enable the interrupt using t1en. the g bit must also be set. the interrupt service routine must reset the pending flag and perform whatever processing is desired. - rbit t1pnd, t1cntrl ; t1pnd equals 3 - ld t1ralo, #6fh ; high (low) for 1.391ms (1mhz clock) - ld t1rahi, #05h 21 www.fairchildsemi.com ace1202 product family rev. b.1 ace1202 product family arithmetic controller engine (acex?) for low power applications 5.3 mode 2: external event counter mode the external event counter mode operates similarly to the pwm mode; however, the timer is not clocked by the instruction clock but by transitions of the t1 input signal. the edge is selectable through the t1c1 bit of the t1cntrl register. a block diagram of the timer s external event counter mode of operation is shown in figure 16. the t1 input should be connected to an external device that generates a positive/negative-going pulse for each event. by clocking the timer through t1, the number of positive/negative transitions can be counted therefore allowing software to capture the number of events that occur. the input signal on t1 must have a pulse width equal to or greater than one instruction clock cycle. the counter can be configured to sense either positive-going or negative-going transitions on the t1 pin. the maximum frequency at which transitions can be sensed is one-half the frequency of the instruction clock. as with the pwm mode, when the counter underflows the counter is reloaded from the t1ra register and the count down proceeds from the loaded value. at every underflow, a pending flag (t1pnd) located in the t1cntrl register is set. software must then clear the t1pnd flag and can then load the t1ra register with an alternate value. the counter has one interrupt (tmri1) that is maskable through the t1en bit of the t1cntrl register. however, the core is only interrupted if the t1en bit and the g (global interrupt enable) bit of the sr is set. if interrupts are enabled, the counter will generate an interrupt each time the t1pnd flag is set (whenever timer underflows provided that the pending flag was cleared.) the interrupt service routine is responsible for proper handling of the t1pnd flag and the t1en bit. the following steps show how to properly configure timer 1 to operate in the external event counter mode. for this example, the counter is clocked every falling edge of the t1 input signal. follow the instructions in parentheses to clock the counter every rising edge. data bus 16-bit auto-reload register (t1ra) 16-bit counter (tmr1) t1 underflow interrupt edge selector logic figure 16: external event counter mode 1. configure t1 as an input by clearing bit 2 of portgc. - rbit 2, portgc ; configure g2 as an input 2. initialize t1 to input with pull-up by setting bit 2 of portgd. - sbit 2, portgd ; set g2 high 3. enable the global interrupt enable bit. - sbit 4, status 4. load the initial count into the tmr1 and t1ra registers. when the number of external events is detected, the counter will reach zero; however, it will not underflow until the next event is detected. to count n pulses, load the value n-1 into the registers. if it is only necessary to count the number of occurrences and no action needs to be taken at a particular count, load the value 0xffff into the registers. - ld tmr1lo, #0ffh - ld tmr1hi, #00h - ld t1ralo, #0ffh - ld t1rahi, #00h 5. write the appropriate control value to the t1cntrl register to select external event counter mode, to clock every falling edge, to set the enable bit, to clear the pending flag, and to start the counter. (see table 12 and 13) - ld t1cntrl, #34h (#00h) ; setting the t1c0 bit starts the timer 6. when the counter underflows, the interrupt service routine must clear the t1pnd flag and take whatever action is required once the number of events occurs. if the software wishes to merely count the number of events and the anticipated number may exceed 65,536, the interrupt service routine should record the number of underflows by incrementing a counter in memory. software can then calculate the correct event count. - rbit t1pnd, t1cntrl ; t1pnd equals 3 22 www.fairchildsemi.com ace1202 product family rev. b.1 ace1202 product family arithmetic controller engine (acex?) for low power applications 5.4 mode 3: input capture mode in the input capture mode, the timer is used to measure elapsed time between edges of an input signal. once the timer is configured for this mode, the timer starts counting down immediately at the instruction clock rate. the timer 1 will then transfer the current value of the tmr1 register into the t1ra register as soon as the selected edge of t1 is sensed. the input signal on t1 must have a pulse width equal to or greater than one instruction clock cycle. at every t1ra capture, software can then store the values into ram to calculate the elapsed time between edges on t1. at any given time (with proper consider- ation of the state of t1) the timer can be configured to capture on positive-going or negative-going edges. a block diagram of the timer s input capture mode of operation is shown in figure 17. the timer has one interrupt (tmri1) that is maskable through the t1en bit of the t1cntrl register. however, the core is only interrupted if the t1en bit and the g (global interrupt enable) bit of the sr is set. the input capture mode contains two interrupt pending flags 1) the tmr1 register capture in t1ra (t1pnd) and 2) timer underflow (t1c0). if interrupts are enabled, the timer will generate an interrupt each time a pending flag is set (provided that the pending flag was previously cleared.) the interrupt service routine is responsible for proper handling of the t1pnd flag, t1c0 flag, and the t1en bit. for this operating mode, the t1c0 control bit serves as the timer underflow interrupt pending flag. the timer 1 interrupt service routine must read both the t1pnd and t1c0 flags to determine the cause of the interrupt. a set t1c0 flag means that a timer underflow occurred whereas a set t1pnd flag means that a capture occurred in t1ra. it is possible that both flags will be found set, meaning that both events occurred at the same time. the interrupt service routine should take this possibility into consideration. because the t1c0 bit is used as the underflow interrupt pending flag, it is not available for use as a start/stop bit as in the other modes. the tmr1 register counts down continuously at the instruction clock rate starting from the time that the input capture mode is selected. (see table 12 and 13) to stop the timer from running, you must change the mode to an alternate mode (pwm or external event counter) while resetting the t1c0 bit. the input pins can be independently configured to sense positive- going or negative-going transitions. the edge sensitivity of pin t1 is controlled by bit t1c1 as indicated in table 13. the edge sensitivity of a pin can be changed without leaving the input capture mode even while the timer is running. this feature allows you to measure the width of a pulse received on an input pin. data bus 16-bit input capture register (t1ra) 16-bit timer (tmr1) t1 capture interrupt edge selector logic instruction clock underflow interrupt figure 17: input capture mode for example, the t1 pin can be programmed to be sensitive to a positive-going edge. when the positive edge is sensed, the tmr1 register contents is transferred to the t1ra register and a timer 1 interrupt is generated. the timer 1 interrupt service routine records the contents of the t1ra register, changes the edge sensitivity from positive to negative-going edge, and clears the t1pnd flag. when the negative-going edge is sensed another timer 1 interrupt is generated. the interrupt service routine reads the t1ra register again. the difference between the previous reading and the current reading reflects the elapsed time between the positive edge and negative edge of the t1 input signal i.e. the width of the positive-going pulse. remember that the timer1 interrupt service routine must test the t1c0 and t1pnd flags to determine the cause of the interrupt. if the t1c0 flag caused the interrupt, the interrupt service routine should record the occurrence of an underflow by incrementing a counter in memory or by some other means. the software that calculates the elapsed time between captures should take into account the number of underflow that occurred when making its calculation. the following steps show how to properly configure timer 1 to operate in the input capture mode. 1. configure t1 as an input by clearing bit 2 of portgc. - rbit 2, portgc ; configure g2 as an input 2. initialize t1 to input with pull-up by setting bit 2 of portgd. - sbit 2, portgd ; set g2 high 3. enable the global interrupt enable bit. - sbit 4, status 4. with the timer stopped, load the initial time into the tmr1 register (typically the value is 0xffff.) - ld tmr1lo, #0ffh - ld tmr1hi, #00h 5. write the appropriate control value to the t1cntrl register to select input capture mode, to sense the appropriate edge, to set the enable bit, and to clear the pending flags. (see table 12 and 13) - ld t1cntrl, #64h ; t1c1 is the edge select bit 6. as soon as the input capture mode is enabled, the timer starts counting. when the selected edge is sensed on t1, the t1ra register is loaded and a timer 1 interrupt is triggered. 23 www.fairchildsemi.com ace1202 product family rev. b.1 ace1202 product family arithmetic controller engine (acex?) for low power applications figure 18: difference capture mode data bus 16-bit input capture register (t1ra) 16-bit timer (tmr1) t1 capture interrupt edge selector logic instruction clock underflow interrupt difference logic 5.5 mode 4: difference input capture mode the difference input capture mode works similarly to the stan- dard input capture mode. however, for the difference input capture the timer automatically captures the elapsed time be- tween the selected edges without the core needing to perform the calculation. for example, the standard input captrue mode requires that the timer be configured to capture a particular edge (rising or falling) at which time the timer's value is copied into the capture register. if the elapsed time is required, software must move the captured data into ram and reconfigure the input capture mode to capture on the next edge (rising or falling). software must then subtract the difference between the two edges to yield useful information. the difference capture mode eliminates the need for software intervention and allows for capturing very short pulse or cycle widths. it can be configured to capture the elapsed time between: 1. positive to negative-going edges 2. positive to positive-going edges 3. negative to positive-going edges 4. negative to negative-going edges once configured, the difference capture timer waits for the first selected edge. when the edge transition has occurred, the 16-bit timer starts counting up based every instruction clock cycle. it will continue to count until the second selected edge transition occurs at which time the timer stops and stores the elapse time into the t1ra register. software can now read the differnce between transitions directly without using any processor resources. however, like the stan- dard input capture mode both the capture (t1pnd) and the underflow (t1c0) flags must be monitored and handled appropri- ately. this feature allows the acex microcontroller to capture very small pulses where standard microcontrollers might have missed cycles due to the limited bandwidth. 24 www.fairchildsemi.com ace1202 product family rev. b.1 ace1202 product family arithmetic controller engine (acex?) for low power applications 6.0 timer 0 timer 0 is a 12-bit free running idle timer. upon power-up or any reset, the timer is reset to 0x000 and then counts up continuously based on the instruction clock of 1mhz (1 s). software cannot read from or write to this timer. however, software can monitor the timer s pending (t0pnd) bit that is set every 8192 cycles (initially 4096 cycles after a reset). the t0pnd flag is set every other time the timer overflows (transitions from 0xfff to 0x000) through a divide-by-2 circuit. after an overflow, the timer will reset and restart its counting sequence. software can either poll the t0pnd bit or vector to an interrupt subroutine. in order to interrupt on a t0pnd, software must be sure to enable the timer 0 interrupt enable (t0inten) bit in the timer 0 control (t0cntrl) register and also make sure the g bit is set in sr. once the timer interrupt is serviced, software should reset the t0pnd bit before exiting the routine. timer 0 supports the following functions: 1. exiting from idle mode (see section 17.0 for details.) 2. start up delay from halt mode 3. watchdog pre-scaler (see section 7.0 for details.) the t0inten bit is a read/write bit. if set to 0, interrupt requests from the timer 0 are ignored. if set to 1, interrupt requests are accepted. upon reset, the t0inten bit is reset to 0. the t0pnd bit is a read/write bit. if set to 1, it indicates that a timer 0 interrupt is pending. this bit is set by a timer 0 overflow and is figure 19: timer 0 control register (t0cntrl) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wkinten x x x x x t0pnd t0inten figure 20: watchdog server register (wdsvr) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00011011 reset by software or system reset. the wkinten bit is used in the multi-input wakeup/interrupt block. see section 8 for details. 7.0 watchdog timer the watchdog timer is used to reset the device and safely recover in the rare event of a processor runaway condition. the 12-bit timer 0 is used as a pre-scaler for watchdog timer. the watchdog timer must be serviced before every 61,440 cycles but no sooner than 4096 cycles since the last watchdog reset. the watchdog is serviced through software by writing the value 0x1b to the watchdog service (wdsvr) register (see figure 20). the part resets automatically if the watchdog is serviced too frequent, or not frequent enough. the watchdog timer must be enabled through the watchdog enable bit (wden) in the initialization register. the wden bit can only be set while the device is in programming mode. once set, the watchdog will always be powered-up enabled. software cannot disable the watchdog. the watchdog timer can only be disabled in programming mode by resetting the wden bit as long as the memory write protect (wdis) feature is not enabled. warning ensure that the watchdog timer has been serviced before enter- ing idle mode because it remains operational during this time. 25 www.fairchildsemi.com ace1202 product family rev. b.1 ace1202 product family arithmetic controller engine (acex?) for low power applications 8.0 hardware bit-coder (ace1202-2 only) the ace1202-2 contains a dedicated hardware bit-encoding peripheral block, hardware bit-coder (hbc), for ir/rf data transmission (see figure 21.) the hbc is completely software programmable and can be configured to emulate various bit- encoding formats. the software developer has the freedom to encode each bit of data into a desired pattern and output the encoded data at the desired frequency through either the g2 or g5 output (tx) ports. the hbc contains six 8-bit memory-mapped configuration regis- ters pscale, hpattern, lpattern, bpsel, hbcntrl, and dat0. the registers are used to select the transmission fre- quency, store the data bit-encoding patterns, configure the data bit-pattern/frame lengths, and control the data transmission flow. to select the ir/rf transmission frequency, an 8-bit divide constant must be written into the ir/rf pre-scalar (pscale) register. the ir/rf transmission frequency generator divides the 1mhz instruction clock down by 4 and the pscale register is used to select the desired ir/rf frequency shift. together, the transmission frequency range can be configured between 976hz (pscale = 0xff) and 125khz (pscale = 0x01). upon a reset, the pscale register is initialized to zero disabling the ir/rf transmission frequency generator. however, once the pscale register is programmed, the desired ir/rf frequency is main- tained as long as the device is powered. once the transmission frequency is selected, the data bit-encod- ing patterns must be stored in the appropriate registers. the hbc contains two 8-bit bit-encoding pattern registers, high-pattern (hpattern) and low-pattern (lpattern). the encoding pat- tern stored in the hpattern register is transmitted when the data bit value to be encoded is a 1. similarly, the pattern stored in the lpattern register is transmitted when the data bit value to be encoded is a 0. the hbc transmits each encoded pattern msb first. the number of bits transmitted from the hpattern and lpattern registers is software programmable through the bit period configuration (bpsel) register (see figure 22). during the transmission of hpattern, the number of bits transmitted is configured by bph[2:0] (bpsel[2:0]) while bpl[2:0] (bpsel[5:3]) configures the number of transmitted bits for the lpattern. the hbc allows from 2 (0x1) to 8 (0x7) encoding pattern bits to be transmitted from each register. upon a reset, bpsel is initially 0 disabling the hbc from transmitting pattern bits from either register. the data (dat0) register is used to store up to 8 bits of data to be encoded and transmitted by the hbc. this data is shifted, bit by bit, msb to lsb into a 1-bit decision register. if the active bit shifted into the decision register is 1, the pattern in the hpattern register is shifted out of the output port. similarly, if the active bit is 0 the pattern in the lpattern register is shifted out. the hbc control (hbcntrl) register is used to configure and control the data transmission. hbcntrl is divided in 5 different controlling signal frame[2:0], iosel, txbusy, start/stop, and ocflag (see figure 23.) frame[2:0] selects the number of bits of dat0 to encode and transmit. the hbc allows from 2 (0x1) to 8 (0x7) dat0 bits to be encoded and transmitted. upon a reset, frame is initialized to zero disabling the dat0 s decision register transmitting no data. the iosel signal selects the transmission to output (tx) through either port g2 or g5. if iosel is 1, g5 is selected as the output port otherwise g2 is selected. the txbusy signal is read only and is used to inform software that a transmission is in progress. txbusy goes high when the encoded data begins to shift out of the output port and will remains high during each consecutive dat0 frame bit transmission (see figure 25). the hbc will clear the txbusy signal when the last dat0 encoded bit of the frame is transmitted and the stop signal is 0. the start / stop signal controls the encoding and transmission process for each data frame. when software sets the start / stop bit the dat0 frame transmission process begins. the start signal will remain high until the beginning of the last encoded dat0 frame bit transmission. the hbc then clears the start / stop bit allowing software to either continue with a new dat0 frame transmission or stop the transmission all together (see figure 25). if txbusy is 0 when the start signal is enabled, a synchronization period occurs before any data is transmitted lasting the amount of time to transmit a 0 encoded bit (see figure 24). the ocflag signal is read only and goes high when the last encoded bit of the dat0 frame is transmitting. the ocflag signal is used to inform software that the dat0 frame transmission operation is completing (see figure 25). if multiple dat0 frames are to be transmitted consecutively, software should poll the ocflag signal for a 1. once ocflag is 1, dat0 must be reload and the start / stop bit must be restored to 1 in order to begin the new frame transmission without interruptions (the synchroni- zation period). since ocflag remains high during the entire last encoded dat0 frame bit transmission, software should wait for the hbc to clear the ocflag signal before polling for the new ocflag high pulse. if new data is not reloaded into dat0 and the start signal (stop is active) is not set before the ocflag is 0, the transmission process will end (txbusy is cleared) and a new process will begin starting with the synchronization period. figure 24 and 25 shows how the hbc performs its data encoding. in the example, two frames are encoded and transmitted consecu- tively with the following bit encoding format specification: 1. transmission frequency = 62.5khz 2. data to be encoded = 0x52, 0x92 (all 8-bits) 3. each bit should be encoded as a 3-bit binary value, 1 = 110b and 0 = 100b 4. transmission output port : g2 to perform the data transmission, software must first initialize the pscale, bpsel, hpattern, lpattern, and dat0 registers with the appropriate values. ld pscale, #03h ; (1mhz 4) 4 = 62.5khz ld bpsel, #012h ; bph = 2, bpl = 2 (3 bits each) ld hpattern, #0c0h ; hpattern = 0xc0 ld lpattern, #090h ; lpattern = 0x90 ld dat0, #052h ; dat0 = 0x52 once the basic registers are initialized, the hbc can be started. (at the same time, software must set the number of data bits per data frame and select the desired output port.) ld hbcntrl, #27h ; start / stop = 1, frame = 7, iosel = 0 26 www.fairchildsemi.com ace1202 product family rev. b.1 ace1202 product family arithmetic controller engine (acex?) for low power applications after the hbc has started, software must then poll the ocflag for a high pulse and restore the dat0 register and the start signal to continue with the next data transmission. loop_hi: ifbit ocflag, hbcntrl ; wait for ocflag = 1 jp nxt_frame jp loop_hi nxt_frame: ld dat0, #092h ; dat0 = 0x92 sbit start, hbcntrl ; start / stop = 1 if software is to proceed with another data transmission, the ocflag must be zero before polling for the next ocflag high pulse. however, since the specification in the example requires no other data transmission software can proceed as desired. loop_lo: ifbit ocflag, hbcntrl ; wait for ocflag = 0 jp loop_lo etc. ; program proceeds as desired pscale lpattern hpattern down counter dat0 ir/rf clock 3 3 3 3 frame[2:0] [hbcntrl] bpl[2:0] [bpsel] bph[2:0] [bpsel] b7 shiftclk noshift rfclk rfclk stopshift stopshift b7 b7 a b y ab y fixed clock divider by 4 8 g2 g5 iosel hbcntrl[6] [pscale] cpu clock ocflag ocflag hbcntrl[7] sync logic start/stop hbcntrl[5] txbusy hbcntrl[4] figure 21: hardware bit-coder (hbc) block diagram figure 22: bit period configuration (bpsel) register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 bpl[2:0] bph[2:0] figure 23: hbc control (hbcntrl) register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ocflag iosel start/stop txbusy 0 frame[2:0] 27 www.fairchildsemi.com ace1202 product family rev. b.1 ace1202 product family arithmetic controller engine (acex?) for low power applications figure 24: hbc signals for one byte message in pwm format ocflag sync period shiftclk bit 7 dat0 g2/g5 output ir/rf clock condition: bpsel = 0x12 [ "1", " 0 " = 3 * ir/rf clocks] dat0 = 0x52 no. bit to encode = 8 (hbcntrl = xxxx0111b) "0" "1" "1" "0" "1" "0" "0" "0" start/stop txbusy "0" figure 25: sending series of encoded messages ocflag shiftclk bit 7 dat0 g2/g5 output ir/rf clock conditions: bpsel = 0x12 [ "1", " 0 " = 3 * ir/rf clocks] dat0 = 0x52 , 0x92 no. bit to encode = 8 (hbcntrl = xxxx0111b) start/stop txbusy "0" "1" "1" "0" "1" "0" "0" "0" "1" "0" "1" "0" "0" "0" "0" "1" software must set the start bit while ocflag is set in order to send another message without introducing a delay. stop bit clear, transmission ends. "0" sync period 28 www.fairchildsemi.com ace1202 product family rev. b.1 ace1202 product family arithmetic controller engine (acex?) for low power applications 9.0 multi-input wakeup/interrupt block the multi-input wakeup (miw)/interrupt contains three memory-mapped registers associated with this circuit: wkedg (wakeup edge), wken (wakeup enable), and wkpnd (wakeup pending). each register has 8-bits with each bit corresponding to an input pins as shown in figure 26. all three registers are initialized to zero upon reset. the wkedg register establishes the edge sensitivity for each of the wake-up input pin: either positive going-edge (0) or negative- going edge (1). the wken register enables (1) or disables (0) each of the port pins for the wakeup/interrupt function. the wakeup i/os used for the wakeup/interrupt function must also be configured as an input pin in its associated port configuration register. however, an interrupt of the core will not occur unless interrupts are enabled for the block via bit 7 of the t0cntrl register (see figure 19) and the g (global interrupt enable) bit of the sr is set. the wkpnd register contains the pending flags corresponding to each of the port pins (1 for wakeup/interrupt pending, 0 for wakeup/interrupt not pending). to use the multi-input wakeup/interrupt circuit, perform the steps listed below. performing the steps in the order shown will prevent false triggering of a wakeup/interrupt condition. this same procedure should be used following any type of reset because the wakeup inputs are left floating after resets resulting in unknown data on the port inputs. 1. clear the wken register. - clr wken 2. if necessary, write to the port configuration register to select the desired port pins to be configured as inputs. - rbit 4, portgc ; g4 3. if necessary, write to the port data register to select the desired port pins input state. - sbit 4, portgd ; pull-up 4. write the wkedg register to select the desired type of edge sensitivity for each of the pins used. - ld wkedg, #0ffh ; all negative-going edges 5. clear the wkpnd register to cancel any pending bits. - clr wkpnd 6. set the wken bits associated with the pins to be used, thus enabling those pins for the wakeup/interrupt function. - ld wken, #10h ; enabling g4 once the multi-input wakeup/interrupt function has been config- ured, a transition sensed on any of the i/o pins will set the corresponding bit in the wkpnd register. the wkpnd bits , where the corresponding enable (wken ) bits are set, will bring the device out of the halt mode and can also trigger an interrupt if interrupts are enabled. the interrupt service routine can read the wkpnd register to determine which pin sensed the interrupt. the interrupt service routine or other software should clear the pending bit. the device will not enter halt mode as long as a wkpnd pending bit is pending and enabled. the user has the responsibility of clearing the pending flags before attempting to enter the halt mode. upon reset, the wkedg register is configured to select positive- going edge sensitivity for all wakeup inputs. if the user wishes to change the edge sensitivity of a port pin, use the following proce- dure to avoid false triggering of a wakeup/interrupt condition. 1. clear the wken bit associated with the pin to disable that pin. 2. write the wkedg register to select the new type of edge sensitivity for the pin. 3. clear the wkpnd bit associated with the pin. 4. set the wken bit associated with the pin to re-enable it. portg provides the user with three fully selectable, edge sensi- tive interrupts that are all vectored into the same service subrou- tine. the interrupt from portg shares logic with the wakeup circuitry. the wken register allows interrupts from portg to be individually enabled or disabled. the wkedg register specifies the trigger condition to be either a positive or a negative edge. the wkpnd register latches in the pending trigger conditions. since portg is also used for exiting the device from the halt mode, the user can elect to exit the halt mode either with or without the interrupt enabled. if the user elects to disable the interrupt, then the device restarts execution from the point at which it was stopped (first instruction cycle of the instruction following halt mode entrance instruction). in the other case, the device finishes the instruction that was being executed when the part was stopped and then branches to the interrupt service routine. the device then reverts to normal operation. data bus 7 0 wken[7:0] 0 7 wkedg[0:7] wkpnd[0:7] g7 g0 edgei wkout wkinten 11 figure 27: multi-input wakeup (miw) block diagram figure 26: multi-input wakeup (miw) register bit assignments wkedg, wken, wkpnd bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 11 g7 11 g6 g5 g4 g3 g2 g1 g0 11 available only on the 14-pin package option 12 wkinten: bit 7 of t0cntrl 29 www.fairchildsemi.com ace1202 product family rev. b.1 ace1202 product family arithmetic controller engine (acex?) for low power applications 10.0 i/o port the eight i/o pins (six on 8-pin package option) are bi-directional (see figure 28) with the exception of g3 which is always an input with weak pull-up. the bi-directional i/o pins can be individually configured by software to operate as high-impedance inputs, as inputs with weak pull-up, or as push-pull outputs. the operating state is determined by the contents of the corresponding bits in the data and configuration registers. each bi-directional i/o pin can be used for general purpose i/o, or in some cases, for a specific alternate function determined by the on-chip hardware. 10.1 i/o registers the i/o pins (g0-g7) have three memory-mapped port registers associated with the i/o circuitry: a port configuration register (portgc), a port data register (portgd), and a port input register (portgp). portgc is used to configure the pins as inputs or outputs. a pin may be configured as an input by writing a 0 or as an output by writing a 1 to its corresponding portgc bit. if a pin is configured as an output, its portgd bit represents the state of the pin (1 = logic high, 0 = logic low). if the pin is configured as an input, its portgd bit selects whether the pin is a weak pull- up or a high-impedence input. table 14 provides details of the port configuration options. the port configuration and data registers can both be read from or written to. reading portgp returns the value of the port pins regardless of how the pins are configured. since this device supports miw, portg inputs have schmitt triggers. table 14: i/o configuration options configuration bit data bit port pin configuration 0 0 high-impedence input (tri-state input) 0 1 input with pull-up (weak one input) 1 0 push-pull zero output 1 1 push-pull one output figure 28: portg logic diagram gxpullen gxbufen gxout gxin padgx figure 29: i/o register bit assignments (portgc,portgd, portgd) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 13 g7 13 g6 g5 g4 14 g3 g2 g1 g0 13 available only on the 14-pin package option 14 g3 is always an input with weak pull-up 30 www.fairchildsemi.com ace1202 product family rev. b.1 ace1202 product family arithmetic controller engine (acex?) for low power applications 11.0 in-circuit programming specification 15,16 the acex microcontroller supports in-circuit programming of the internal data eeprom, code eeprom, and the initialization registers. an externally controlled four wire interface consisting of a load control pin (g3), a serial data shift-in input pin (g4), a serial data shift-out output pin (g2), and a clock pin (g1) is used to access the on-chip memory locations. communication between the acex microcontroller and the external programmer is made through a 32- bit command and response word described in table 15. the serial data timing for the four-wire interface is shown in figure 31 and the programming protocol is shown in figure 30. 11.1 write sequence the external programmer brings the acex microcontroller into programming mode by applying a super voltage level to the load pin. the external programmer then needs to set the load pin to 5v before shifting in the 32-bit serial command word using the shift_in and clock signals. by definition, bit 31 of the command word is shifted in first. at the same time, the acex microcontroller shifts out the 32-bit serial response to the last command on the shift_out pin. it is recommended that the external programmer samples this signal t access (500ns) after the rising edge of the clock signal. the serial response word, sent immediately after entering program- ming mode, contains indeterminate data. after 32 bits have been shifted into the device, the external programmer must set the load signal to 0v, and then apply two clock pulses as shown in figure 30 to complete program cycle. the shift_out pin acts as the handshaking signal between the device and programming hardware once the load signal is brought low. the device sets shift_out low by the time the programmer has sent the second rising edge during the load = 0v phase (if the timing specifications in figure 30 are obeyed). the device will set the r bit of the status register when the write operation has completed. the external programmer must wait for the shift_out pin to go high before bringing the load signal to 5v to initiate a normal command cycle. 11.2 read sequence when reading the device after a write, the external programmer must set the load signal to 5v before it sends the new command word. next, the 32-bit serial command word (for during a read) should be shifted into the device using the shift_in and the clock signals while the data from the previous command is serially shifted out on the shift_out pin. after the read com- mand has been shifted into the device, the external programmer must, once again, set the load signal to 0v and apply two clock pulses as shown in figure 30 to complete read cycle. data from the selected memory location, will be latched into the lower 8 bits of the command word shortly after the second rising edge of the clock signal. writing a series of bytes to the device is achieved by sending a series of write command words while observing the devices handshaking requirements. reading a series of bytes from the device is achieved by sending a series of read command words with the desired addresses in sequence and reading the following response words to verify the correct address and data contents. the addresses of the data eeprom and code eeprom loca- tions are the same as those used in normal operation. powering down the device will cause the part to exit programming mode. table 15: 32-bit command and response word bit number input command word output response word bits 31 C 30 must be set to 0 x bit 29 set to 1 to read/write data eeprom, or the x initialization registers, otherwise 0 bit 28 set to 1 to read/write code eeprom, x otherwise 0 bits 27 C 25 must be set to 0 x bit 24 set to 1 to read, 0 to write x bits 23 C 19 must be set to 0 x bits 18 C 8 address of the byte to be read or written same as input command word bits 7 C 0 data to be programm ed or zero if data is to be read programmed data or data read at specified address 15 for further information see application note an-8005. 16 during in-circuit programming, g5 must be either not connected or driven high. 31 www.fairchildsemi.com ace1202 product family rev. b.1 ace1202 product family arithmetic controller engine (acex?) for low power applications figure 31: serial data timing figure 30: programming protocol 16 load (g3) clock (g1) shift_in (g4) shift_out (g2) (in write mode) bit 31 bit 30 bit 0 bit 31 shift_out (g2) (in read mode) t sv1 t sv2 a a: start of programming cycle 32 clock pulses t load2 busy ready a t load4 t load3 t ready busy low by 2nd clock pulse enter prog. mode t load1 valid valid shift_out (g2) shift_in (g4) clock (g1) t hi t lo t dis t dih t doh t dos t access 32 www.fairchildsemi.com ace1202 product family rev. b.1 ace1202 product family arithmetic controller engine (acex?) for low power applications 12.0 brown-out/low battery detect circuit the brown-out reset (bor) and low battery detect (lbd) circuits on the acex microcontroller have been designed to offer two types of voltage reference comparators. the sections below will describe the functionality of both circuits. figure 32: bor/lbd block diagram zero before rising back to operating range. the brown-out reset can be thought of as a supplement function to the power-on reset when v cc does not fall below ~1.5v. the power-on reset circuit works best when v cc starts from zero and rises sharply. so in applications where v cc is not constant, the bor will give added device stability. the bor circuit must be enabled through the bor enable bit (boren) in the initialization register. the boren bit can only be set while the device is in programming mode. once set, the bor will always be powered-up enabled. software cannot disable the bor. the bor can only be disabled in programming mode by resetting the boren bit as long as the global write protect (wdis) feature is not enabled. 18 bor is not available on the p.n. ace1202b/ace12022b device 12.2 low battery detect the low battery detect (lbd) circuit allows software to monitor the v cc level at the lower voltage ranges. lbd has an eight level software programmable voltage reference threshold that can be changed on the fly. once v cc falls below the selected threshold, the lbd flag in the lbd control register is set. the lbd flag will hold its value until v cc rises above the threshold. (see table 16) the lbd bit is read only. if lbd is 0, it indicates that the v cc level is higher than the selected threshold. if lbd is 1, it indicates that the v cc level is below the selected threshold. the threshold level can be adjusted up to eight levels using the three trim bits (bat_trim[2:0]) of the lbd control register. the lbd flag does not cause any hardware actions or an interruption of the processor. it is for software monitoring only. the lbd function is disabled during halt/idle mode. after exiting halt/idle, software must wait at least 10 s before reading the lbd bit to ensure that the internal circuit has stabi- lized. 7 6 5 4 3 2 1 0 adjust reference voltage lbd control register + _ + _ to reset logic vcc bor lbd 1 0 s 1.8v 2.2v blsel 17 table 16: lbd control register definition bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bat_trim[2:0] 0 x x x lbd voltage reference level bat_trim[2] bat_trim[1] bat_trim[0] range ( 20%) 1 0 0 0 2.9 - 3.0 2 0 0 1 2.8 - 2.9 3 0 1 0 2.7 - 2.8 4 0 1 1 2.6 - 2.7 5 1 0 0 2.5 - 2.6 6 1 0 1 2.4 - 2.5 7 1 1 0 2.3 - 2.4 8 1 1 1 2.2 - 2.3 17 see figure 14 for information on blsel. 12.1 brown out reset 18 the brown-out reset (bor) function is used to hold the device in reset when v cc drops below a fixed threshold. (see bor electri- cal characteristics for threshold voltage.) while in reset, the device is held in its initial condition until v cc rises above the threshold value. shortly after v cc rises above the threshold value, an internal reset sequence is started. after the reset sequence, the core fetches the first instruction and starts normal operation. on the devices, the bor should be used in situations when v cc rises and falls slowly and in situations when v cc does not fall to 33 www.fairchildsemi.com ace1202 product family rev. b.1 ace1202 product family arithmetic controller engine (acex?) for low power applications 13.0 reset block when a reset sequence is initiated, all i/o registers will be reset setting all i/os to high-impedence inputs. the system clock is restarted after the required clock start-up delay. a reset is gener- ated by any one of the following three conditions: power-on reset (as described in section 14.0) brown-out reset (as described in section 12.1) watchdog reset (as described in section 7.0) external reset 18 (as described in section 14.0) 18 available only on the 14-pin package option. 14.0 power-on-reset the power-on reset (por) circuit is guaranteed to work if the rate of rise of v cc is no slower than 10ms/1volt. the por circuit was designed to respond to fast low to high transitions between 0v and v cc . the circuit will not work if v cc does not drop to 0v before the next power-up sequence. in applications where 1) the v cc rise is slower than 10ms/1 volt or 2) v cc does not drop to 0v before the next power-up sequence the external reset option should be used. the external reset provides a way to properly reset the acex microcontroller if por cannot be used in the application. the external reset pin contains an internal pull-up resistor. therefore, to reset the device the reset pin should be held low for at least 2ms so that the internal clock has enough time to stabilize. 15.0 clock the acex microcontroller has an on-board oscillator trimmed to a frequency of 2mhz who is divided down by two yielding a 1mhz frequency. (see ac electrical characteristics.) upon power-up, the on-chip oscillator runs continuously unless entering halt mode or using an external clock source. if required, an external oscillator circuit may be used depending on the states of the cmode bits of the initialization register. (see table 17) when the device is driven using an external clock, the clock input to the device (g1/cki) can range between dc to 4mhz. for external crystal configuration, the output clock (cko) is on the g0 pin. (see figure 34) if an external crystal or rc is used, internally the input frequency (cki) is divided-down by four to yield the corresponding instruction clock. if the device is configured for an external square clock, it will not be divided. table 17: cmodex bit definition cmode[1] cmode[0] clock type 0 0 internal 1 mhz clock 0 1 external square clock 1 0 external crystal/resonator 1 1 external rc clock figure 33: bor and por circuit relationship diagram v cc (pin 8) bor reset circuit output global reset to logic external reset pin (14-pin only) b a output por (pin 7) output v cc time bor output 1.75 0 v cc v cc 0 por output por output pulse 1.8v 0 v cc v cc 5.0v 0 the reset circuit will trigger when inputs a or b transition from high to low. at that time the global reset signal will go high which will reset all controller logic. the global reset will go high and stay high for around 1 s. 34 www.fairchildsemi.com ace1202 product family rev. b.1 ace1202 product family arithmetic controller engine (acex?) for low power applications figure 35: halt register definition bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 undefined undefined undefined undefined undefined undefined eidle ehalt figure 34: crystal (a) and rc (b) oscillator diagrams 33pf 33pf 1m cki (g1) cko (g0) a) c v cc r cki (g1) cko (g0) b) normal mode ld halt, #01h halt multi-input wakeup ld pmc, #00h resume normal mode normal mode clr wken ld halt, #02h idle ld pmc, #00h resume normal mode timer 0 overflow 15.0 halt mode the halt mode is a power saving feature that almost completely shuts down the device for current conservation. the device is placed into halt mode by setting the halt enable bit (ehalt) of the halt register through software using only the ld m, # instruction. ehalt is a write only bit and is automatically cleared upon exiting halt. when entering halt, the internal oscillator and all the on-chip systems including the lbd and the bor circuits are shut down. the device can exit halt mode only by the miw circuit. there- fore, prior to entering halt mode, software must configure the miw circuit accordingly. (see section 9) after a wakeup from halt, a 1ms start-up delay is initiated to allow the internal oscillator to stabilize before normal execution resumes. immedi- ately after exiting halt, software must clear the power mode clear (pmc) register by only using the ld m, # instruction. (see figure 36) 17.0 idle mode in addition to the halt mode power saving feature, the device also supports an idle mode operation. the device is placed into idle mode by setting the idle enable bit (eidle) of the halt register through software using only the ld m, # instruction. eidle is a write only bit and is automatically cleared upon exiting idle. the idle mode operation is similar to halt except the internal oscillator, the watchdog, and the timer 0 remain active while the other on-chip systems including the lbd and the bor circuits are shut down. the device automatically wakes from idle mode by the timer 0 overflow every 8192 cycles (see section 6). before entering idle mode, software must clear the wken register to disable the miw block. once a wake from idle mode is triggered, the core will begin normal operation by the next clock cycle. immediately after exiting idle mode, software must clear the power mode clear (pmc) register by using only the "ld m, #" instruction. (see figure 37) figure 36: recommended halt flow figure 37: recommended idle flow 35 www.fairchildsemi.com ace1202 product family rev. b.1 ace1202 product family arithmetic controller engine (acex?) for low power applications ordering information (ace1202) part number core type max. # program operating voltage temperature range package tape & i/os memory size range reel 0 1 2 8 1k 2k 1.8 2.2 2.7 0 to -40 to -40 to 8-pin 14-pin 8-pin 14-pin 5.5v 5.5v 5.5v 70 c +85c +125 c soic soic dip dip ace1202m8 x x x x x x ace1202m8x x x x x x x x ace1202m x x x x x x ace1202mx x x x x x x x ace1202n x x x x x x ace1202n14 x x x x x x ace1202em8 x x x x x x ace1202em8x x x x x x x x ace1202em x x x x x x ace1202emx x x x x x x x ace1202en x x x x x x ace1202en14 x x x x x x ace1202vm8 x x x x x x ace1202vm8x x x x x x x x ace1202vm x x x x x x ace1202vmx x x x x x x x ace1202vn x x x x x x ace1202vn14 x x x x x x ace1202bm8 x x x x x x ace1202bm8x x x x x x x x ace1202bm x x x x x x ace1202bmx x x x x x x x ace1202bn x x x x x x ace1202bn14 x x x x x x ace1202bem8 x x x x x x ace1202bem8x x x x x x x x ace1202bem x x x x x x ace1202bemx x x x x x x x ace1202ben x x x x x x ace1202ben14 x x x x x x ACE1202BVM8 x x x x x x ACE1202BVM8x x x x x x x x ace1202bvm x x x x x x ace1202bvmx x x x x x x x ace1202bvn x x x x x x ace1202bvn14 x x x x x x ace1202lm8 x x x x x x ace1202lm8x x x x x x x x ace1202lm x x x x x x ace1202lmx x x x x x x x ace1202ln x x x x x x ace1202ln14 x x x x x x 36 www.fairchildsemi.com ace1202 product family rev. b.1 ace1202 product family arithmetic controller engine (acex?) for low power applications ordering information (ace1202-2) part number core type max. # program operating voltage temperature range package tape & i/os memory size range reel 0 1 2 8 1k 2k 1.8 2.2 2.7 0 to -40 to -40 to 8-pin 14-pin 8-pin 14-pin 5.5v 5.5v 5.5v 70 c +85c +125 c soic soic dip dip ace12022m8 x x x x x x ace12022m8x x x x x x x x ace12022m x x x x x x ace12022mx x x x x x x x ace12022n x x x x x x ace12022n14 x x x x x x ace12022em8 x x x x x x ace12022em8x x x x x x x x ace12022em x x x x x x ace12022emx x x x x x x x ace12022en x x x x x x ace12022en14 x x x x x x ace12022vm8 x x x x x x ace12022vm8x x x x x x x x ace12022vm x x x x x x ace12022vmx x x x x x x x ace12022vn x x x x x x ace12022vn14 x x x x x x ace12022bm8 x x x x x x ace12022bm8x x x x x x x x ace12022bm x x x x x x ace12022bmx x x x x x x x ace12022bn x x x x x x ace12022bn14 x x x x x x ace12022bem8 x x x x x x ace12022bem8x x x x x x x x ace12022bem x x x x x x ace12022bemx x x x x x x x ace12022ben x x x x x x ace12022ben14 x x x x x x ace12022bvm8 x x x x x x ace12022bvm8x x x x x x x x ace12022bvm x x x x x x ace12022bvmx x x x x x x x ace12022bvn x x x x x x ace12022bvn14 x x x x x x 37 www.fairchildsemi.com ace1202 product family rev. b.1 ace1202 product family arithmetic controller engine (acex?) for low power applications 8-pin dip (n) order number ace1202(12022, 1202l)n/ace1202(12022)en/ace1202vn ace1202(12022)bn/ace1202(12022)ben/ace1202(12022)bvn package number n08a physical dimensions inches (millimeters) unless otherwise noted 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337) dia + 1234 8765 0.250 - 0.005 (6.35 0.127) 87 0.032 0.005 (0.813 0.127) pin #1 option 2 rad 1 0.145 - 0.200 (3.683 - 5.080) 0.130 0.005 (3.302 0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 90 4 typ 0.100 0.010 (2.540 0.254) 0.040 (1.016) 0.039 (0.991) typ. 20 1 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) pin #1 ident option 1 0.280 min 0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762) max 0.125 (3.175) dia nom 0.009 - 0.015 (0.229 - 0.381) 0.045 0.015 (1.143 0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95 5 0.090 (2.286) (7.112) ident molded small out-line package (m8) order number ace1202(12022, 1202l)m8/ace1202(12022)em8/ace1202vm8 ace1202(12022)bm8/ace1202(12022)bem8/ace1202(12022)bvm8 package number m08a 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.0075 - 0.0098 (0.190 - 0.249) typ. all leads 0.004 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45 38 www.fairchildsemi.com ace1202 product family rev. b.1 ace1202 product family arithmetic controller engine (acex?) for low power applications molded small out-line package (m) order number ace1202(12022, 1202l)m/ace1202(12022)em/ace1202vm ace1202(12022)bm/ace1202(12022)bem/ace1202(12022)bvm package number m14a physical dimensions inches (millimeters) unless otherwise noted 14-pin dip (n14) order number ace1202(12022, 1202l)n14/ace1202(12022)en14/ace1202vn14 ace1202(12022)bn14/ace1202(12022)ben14/ace1202(12022)bvn14 package number n14a 123 4567 14 13 12 11 10 9 8 0.335 - 0.344 (8.509 - 8.788) 0.228 - 0.244 (5.791 - 6.198) 0.010 (0.254) max. lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ typ 0.008 (0.203) 0.014 (0.356) 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.008 - 0.010 (0.203 - 0.254) typ. all leads 0.04 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45 30 typ. 39 www.fairchildsemi.com ace1202 product family rev. b.1 ace1202 product family arithmetic controller engine (acex?) for low power applications fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran ? ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841 acex development tools general information fairchild semiconductor offers different possibilities to evaluate and emulate software written for acex. acex starter kit includes: programmer board simulator software programmer software assembler and manuals cables and samples devices dip programming sockets programmer board: interfaces with a pc through a windows program using the serial communication port. this board is intended for engineering prototype and can be used for small volume production. fairchild offers factory pre-programming and serialization (for justified quantities) for a small additional cost. please refer to your local distributor for details regarding factory programming. simulator: is a windows program able to load, assemble, and debug acex programs. it is possible to place as many breakpoints as needed, trace the program execution in symbolic format, and program a device with the proper options. the acex simulator is available free-of-charge and can be downloaded from fairchild s web site at www.fairchildsemi.com/products/memory/ace acex emulator kit: fairchild also offers a low cost real-time in- circuit emulator kit that includes: emulator board emulator software assembler and manuals power supply dip14 target cable pc cable the acex emulator allows for debugging the program code in a symbolic format. it is possible to place one breakpoint and watch various data locations. it also has built-in programming capability. prototype board kits: fairchild offer two solutions for the simpli- fication of the breadboard operation so that acex applications can be quickly tested. 1) acedemo is can be used for general purpose applications 2) acetxrx for transmitting / receiving (rf, ir, rs232, rs485) applications. acedemo has 8 switches, 8 leds, rs232 voltage translator, buzzer, and a lamp with a small breadboard area. ordering p/ns starter kit: acestart1101 acestart1202 programming adapters: dip8 - acesdip8 dip14 - acesdip14 tssop8 - acestssop8 so8 - acessop8 so14 - acessop15 emulator kit: aceice (110vac) aceice_eu (220vac) prototype boards: acedemo acetxrx (specify rf freq. 433 or 315mhz) |
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